1. Field of the Invention
The present invention relates to a plastic package type semiconductor device, and in particular, to a plastic package type semiconductor device comprising a semiconductor chip and a die pad section (also referred to as a bed section) mounted in close contact on an insulating film by the formation of the film on the die pad inside a lead frame to electrically insulate from each other.
2. Description of the Prior Art
FIG. 1 is a plan view of a lead frame contained in a conventional plastic package type semiconductor device. FIG. 2 is a sectional view showing the structure of the conventional plastic package type semiconductor device viewed along the section A-A' in FIG.1. As shown in the drawings, a die pad 1 is provided on which a semiconductor chip 3 is loaded.
Also provided are a plurality of tab leads 2, specifically, tie bars, and a Jumper lead 7b. As shown in FIG. 2, the Jumper lead 7b is formed in a U-shape to maintain the electrical resistance of the semiconductor chip 3. A bonding wire 9, an insulating adhesive 5 for electrically insulating and bonding tile die pad 1 to the semiconductor chip 3, and a plurality of inner leads 4 are also provided.
In addition, the die pad 1 is divided into two parts by the Jumper lead 7b. The surface of the die pad 1 is normally silver plated. An insulating adhesive 5 is used to bond the semiconductor chip 3 onto the die pad 1.
During the process of attaching the semiconductor chip 3 to the die pad 1, unbonded regions such as voids are formed in the insulating adhesive 5 used for bonding.
When a semiconductor device containing such unbonded regions is used for a long period of time, the silver plating on the die pad 1 migrates into the voids in the insulating adhesive 5 and eventually reaches the under surface (the surface bonded to the insulating adhesive 5) of the semiconductor chip 3.
The problem therefore arises that the electrical insulation between the die pad 1 and the semiconductor chip 3 is broken down by corrosion. In addition, in surface mounted type packages such as an SOP (Small Outline Package), an SOJ (Small Outline J-leaded Package), and the like, as shown in FIG. 3, there are cases in which cracks are produced in the package from VPS (Vapor Phase Soldering) fellow, IR (Infrared Ray) reflow, and the like. These cracks are caused by the absorption of moisture by the package so that steam is formed from heating during reflow, creating sufficient force to form cracks in the package.
The following problems are also associated with the conventional plastic package type semiconductor devices.
Taking a TSOP (Thin Small Outline Package) as a typical example, the thickness of the package has been reduced to the point where, at the present time, a thickness of as low as about 1.0 mm can be provided.
Specifically, FIG. 4 shows the cross sectional configuration of a TSOP in which the thickness A of the plastic mold is 0.28 mm, the thickness B of the semiconductor chip is 0.35 mm, the thickness C of the conductive adhesive is 0.05 mm, the thickness D of the lead frame is 0.15 mm, and the thickness E of the plastic mold is 0.17 mm. The total thickness F of the package is therefore 1.0 mm. However, when the package is to be used as a bank cash card or the like, a thickness of 0.8 mm or less is desirable. A problem therefore exists in that a semiconductor chip with a conventional structure cannot be used for a bank card or the like. If, in order to correct this problem, 0.1 mm is removed from both the top and bottom of the plastic so that the lower side is less than 0.15 mm thick, it is difficult to form the mold. Also, if the thickness of the chip is cut from 0.35 mm to 0.2 mm, the strength of the chip is reduced.
In addition, a reduction in the thickness of the lead frame is impossible from the aspect of strength and handling.
As explained in the foregoing, the problems associated with conventional plastic package type semiconductor devices may be summarized as follows in the conventional plastic package type semiconductor device, as a result of unbonded regions such as voids being formed during the manufacturing process, a breakdown in the electrical insulation in the resulting semiconductor device is possible, and cracking can occur in the package from fellow.
Furthermore, in surface mounted type packages such as an SOP or an SOP or the like, it is impossible to provide a package thickness of less than 1.0 mm which restricts the fields in which the package can be used.